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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
Table 37: MR17 PASR Segment Mask (MA[7:0] = 011h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Segment mask
Note:
1. This table applies for 1Gb to 8Gb devices only.
Table 38: MR17 PASR Segment Mask Definitions
Feature
Segment[7:0] mask
Type
Write-only
OP
OP[7:0]
Definition
0b: refresh enable to the segment: = unmasked (default)
1b: refresh blocked: = masked
Table 39: MR17 PASR Row Address Ranges in Masked Segments
1Gb
2Gb, 4Gb
8Gb
Segment
0
1
2
3
4
5
6
7
OP
0
1
2
3
4
5
6
7
Segment Mask
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
R[12:10]
R[13:11]
000b
001b
010b
011b
100b
101b
110b
111b
R[14:12]
Note:
1. X is “Don’t Care” for the designated segment.
Table 40: Reserved Mode Registers
Mode Reg-
ister
MA
Address
Restriction
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR[18:19]
MR[20:31]
MR[33:39]
MA[7:0]
12h–13h
14h–1Fh
21h–27h
RFU
NVM 1
DNU 1
Reserved
MR[41:47]
29h–2Fh
MR[48:62]
MR[64:126]
MR127
MR[128:190]
MR191
MR[192:254]
MR255
30h–3Eh
40h–7Eh
7Fh
80h–BEh
BFh
C0h–FEh
FFh
RFU
RFU
DNU
RVU 1
DNU
RVU
DNU
Note:
1. NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
52
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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